Broadcom announces switches with Co-Packaged Optics (CPO)
LightCounting releases a research note on this announcement and its implications for the supply chain.
It is official. On January 12th, 2021, Broadcom introduced a line-up of next generation switching ASICs equipped with co-packaged optics. The first 25.6Tb Humboldt will hit the market in the end of 2022 with the 51.2T Bailly to follow a year later, as shown in Figure 1. Broadcom also announced 800G DR8 pluggable transceivers based on a Silicon Photonics Integrated Circuit (PIC) co-packaged with DSP, as well as future plans for co-packaging optics with CPUs and GPUs.
Figure 1: New products announced by Broadcom on January 12, 2021.
Broadcom rarely announces products well ahead of shipments, but this is a special case. The customers will need time to accept the changes. The announcement was not a surprise for Broadcom’s largest customers, but it is a surprise for the broader market, that needs to get on-board. It is also a starting whistle to the competition. The race is on and Broadcom plans to stay in the lead.
LightCounting was not surprised by the announcements either.Our latest forecast for the adoption of co-packaged optics, published in December 2020, was counting on product announcements in 2021. There may be more to come.
Why start with 25Tb?The industry consensus is that co-packaged optics will be necessary on 102Tb switches and possibly on 51Tb. Broadcom starts earlier to give customers more time to kick the tires and test drive the new technology. But there’s a chance that even the 25T CPO solution will deploy in volume since it will offer significant advantages in cost and power.
COBO, CPO and OIF visions of the co-packaged optics come with electrical and optical connectors. Broadcom’s approach solders the opto-chiplets next to the ASIC (on the same substrate). The fibers are probably still detachable, but Broadcom has not offered any details on how it is accomplished, apart from citing 64 I/O fibers per chip with 500Gbps/mm bandwidth density.
It is a future proof design. While, it is possible to manage the loss of electrical sockets on chiplets designed for 100Gb lane speeds, it is a headache and going to higher speeds will be a nightmare. Broadcom’s approach reduces the electrical power loss, enabling direct drive of the opto-chiplets by standard LR SerDes integrated into the ASICs – “the most efficient use of Silicon for the entire system”.
It also signals that Broadcom takes full ownership of the CPO equipped ASIC. If it needs to be replaced, unplug the fibers and remove the whole ASIC. The CPO is powered by external lasers to improve reliability. The lasers come as front facet pluggable modules, just like transceivers today. It is really designed for customers used to plugging in the optics and replacing it as needed.
Broadcom’s customers will also appreciate that the opto-chiplets will be compatible with the optical transceiver MSAs, such as DR4 and DR8. This will enable co-existence of CPO and pluggable transceivers in mega datacenters.
Full text of the research note is available to LightCounting subscribers at: https://www.lightcounting.com/auth/login