Do All Roads Lead to Copackaging of Optics and ASICs?
LightCounting Reports on the IEEE Optical Interconnects Conference
Ali Ghiasi, the general co-chair of the June 2018 IEEE Optical Interconnects Conference held in Santa Fe, opened the conference with a slide titled: “All Roads End in Co-Packaging”, a statement that portends the eventual end of pluggable optical modules. This, along with 100 Gb/s signaling, were the two main themes of the conference.
In the chart below, Ali suggested that the steady ramp to higher electrical signaling speeds on boards and backplanes will end with 100 Gb/s. Pluggable modules and passive DAC assemblies will be practical at 100G/lane electrical, but Ali suggests that will be the final evolution of pluggable modules and conventional backplanes. Cabled backplanes are already an option for years to come, but he suggests that optical IO must reach all the way to the ASIC after 100G. Many other conference speakers and panelists seemed to agree but no one underestimated the great challenges ahead for such a paradigm shift.
Source: Ali Ghiasi, Ghiasi Quantum LLC
In a workshop session on “100 Gb/s Signaling: Enabling Next-Generation Interconnects”, another seven panelists were mostly optimistic about the advantages and timeline to make the next SerDes leap. Brad Booth of Microsoft sees it in 2022/23+ for the 1.6Tb generation. Cisco’s Mark Nowell believes most of the optics industry will go with 4x100G and suggests a QSFP112-DD module for 8x100G in and out. He also noted that 3D memory, a form of co-packaging, took ten years.
Chris Cole of Finisar injected concerns with the “industry obsession with 100g/lane”, noting that for the first time, the industry is splitting its investment between two speeds (50G and 100G). He sees 56G/lane for 4-6 years with more investment still needed at 56G for cost and power. Cole said 7nm CMOS will bring only 20-30% power reduction and there will be no ROI for many years on 100G investments.
Andy Bechtolsheim of Arista Networks is very bullish on 100G SerDes but wants to avoid retimers and flyover cables. He sees a denser chassis, 20% lower power, and lower cost and intense market pressure to get to 100G SerDes ASAP. He suggested OSFP 2 meter DAC simulated by TE Connectivity will support 128 400G ports in a 2RU chassis without co-packaging. While power will be 20% higher, distributed power is easier to cool than co-packaged. No co-packaging is needed to build a 51.2Tb switch.
Andy showed how yield can get clobbered with co-packaging. Yield with terminating large numbers of fibers is much lower than that of the ASIC. The final assembly yield could drop to 50%. Packaging risk must be solved before it becomes the critical path. The only way to improve yield is with repairability. He also noted a warning that perhaps should be obvious: Time to market rules. You cannot add risk and cannot commit to co-packaging until it’s proven. So we must do it the hard way first.